The present invention generally relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter having a ladder type resistor network.
The length of digital data to be processed by a digital-to-analog converter has tended to increase recently. Thus, it is necessary to more precisely determine an analog output level having an increased digital data length.
Referring to FIG.1, there is illustrated a conventional digital-to-analog (hereinafter simply referred to as D/A) converter having a ladder type resistor network. The D/A converter shown in FIG. 1 is a so-called R-2R ladder type converter. The D/A converter in FIG. 1 has a ladder resistor network 1, which is composed of eight stages corresponding to the number of bits of an digital input signal (eight bits in the illustrated case). The ladder resistor network 1 is composed of resistors 2, each having a resistance value R, and weighting resistors 3a-3h, each having a resistance value 2R. The difference between an upper limit voltage AV.sub.DD and a lower limit voltage AV.sub.SS is shared among the weighting resistors 3a-3h so that the weighting resistors 3a-3h support 1/2.sup.8, 1/2.sup.7, . . . , 1/2.sup.1 of the above voltage difference, respectively. Switching circuits 4-11, each having a MOS transistor structure (CMOS inverter), are connected to the weighting resistors 3a-3h, respectively. The digital input signal is composed of eight bits, d.sub.0 -d.sub.7, which are respectively input to the switching circuits 4-11. The values of the bits d.sub.0 -d.sub.7 determine whether the corresponding weighting resistors 3a-3h should be connected to a power supply line of the upper limit voltage AV.sub.DD or a power supply line of the lower limit voltage V.sub.SS. Each of the switches 4-11 is connected to the upper limit voltage line V.sub.DD when the corresponding bit of the digital input data is equal to "1", and on the other hand, connected to the lower limit voltage line V.sub.SS when the corresponding bit is equal to "0".
An analog signal output terminal 20 is provided at a connection node X in the stage of the ladder type resistor network 1 corresponding to the most significant bit d.sub.7 of the digital input signal. A offset level control resistor 21 is connected to a node Y in the stage of the ladder type resistor network 1 corresponding to the least significant bit d.sub.0 of the digital input signal. One end of the resistor 21 opposite to the node Y is fixedly set at the upper limit voltage V.sub.DD.
FIG. 2 is a diagram illustrating a real characteristic of the D/A converter shown in FIG. 1 and a theoretical characteristic thereof. A maximum value of the analog voltage output at the analog signal output terminal 20 is obtained when the digital input signal is equal to #FF (hexadecimal notification), that is, when all the bits d.sub.7 -d.sub.0 are equal to binary ones. On the other hand, a potential greater than the lower limit voltage AV.sub.SS by .DELTA.V (=(AV.sub.DD -AV.sub.SS /2.sup.8) appears at the analog signal output terminal 20 when all the bits d.sub.7 -d.sub.0 are equal to binary zeros.
A case will now be considered in which the output of the switch circuit 11 corresponding to the most significant bit d.sub.7 of the digital input signal changes from the lower limit voltage AV.sub.SS to the upper limit voltage AV.sub.DD, that is, the digital input signal changes from "01111111" (#7F in hexadecimal notification) to "10000000" (#80 in the hexadecimal notification). In this case, the increasing voltage .DELTA.V is decreased to .DELTA.Vx due to the presence of ON resistances of the MOS transistors of the switching circuits 4-10 as well as differences of the resistance values of the resistors 2 and the weighting resistors 3a -3h. In the worst case, the analog voltage for #80 becomes equal to or less than that for #7F.
Half of the voltage difference between AV.sub.DD and AV.sub.SS appears across the weighting resistor 3h corresponding to the most significant bit d.sub.7 of the digital input signal. This voltage appearing across the weighting resistor 3h is greater than the voltages appearing across the other weighting resistors 3a-3g. As a result, even if the resistance value of the resistor 3h has a very small error, this affects the increasing voltage .DELTA.Vx greatly.
In order to avoid the above problem, it is necessary to precisely determine the actual resistance ratio of the ladder type resistor network 1. For this purpose, conventionally, the resistors 2 and the weighting resistors 3a-3h are formed of high-precision resistors. Additionally or alternatively, the MOS transistors of the switching circuits 4-11 are formed of large-size MOS transistors having very small ON resistances.
However, the use of high-precision resistors increases production costs, and the use of large-size MOS transistors decreases integration density and increases the production costs.